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Preface

Purpose and Audience

This book describes, mainly by coding examples, the code patterns that perform well on PowerPC processors. The book will be particularly helpful to compiler developers and application-code specialists who are already familiar with optimizing compiler technology and are looking for ways to exploit the PowerPC architecture. It will also be helpful to application programmers who need to understand and tune the output of PowerPC compilers and to faculty members and graduate students specializing in the study of compilers. We assume that compiler developers have already developed a compiler front-end and are seeking to develop a PowerPC back-end.

The book does not attempt to teach the average programmer how to write a compiler or the accompanying library routines. Readers seeking this kind of information may wish to acquire some of the publications listed in the references.

The book is a companion to Book I of The PowerPC Architecture. Detailed descriptions from The PowerPC Architecture are not repeated except in summary form, although we include several references to sections in the specification. The material and instructions described in Books II and III of The PowerPC Architecture are, in general, not included because they are primarily of interest to operating-system developers.

Code Examples

Where possible and useful, the book includes code examples, generalizations of coding approach, and general advice on issues affecting coding decisions. The examples are primarily in PowerPC assembler code, but they may also show related source code (typically C or Fortran). Most of the code examples are chosen to perform well on a generic PowerPC processor, called a Common Model, although advice on coding for specific PowerPC-processor implementations is sometimes included.

Most code examples are from IBM. A few code examples in Chapter 5, "Clever Examples", have been contributed by non-IBM programmers. A few examples are taken from The PowerPC Architecture or IBM technical papers. The PowerPC extended mnemonics that are used in the code examples are listed in a table at the end of this preface.

Contributors

Writers and Editors:

IBM Editor: Steve Hoxey, IBM Toronto Laboratory
IBM Editor: Faraydon Karim, IBM Microelectronics Division
IBM Editor: Bill Hay, IBM Toronto Laboratory
IBM Editor: Hank Warren, IBM Thomas J. Watson Research Center
Writer: Philip Dickinson, Warthman Associates
Independent Editor: Dennis Allison, Stanford University
HTML Editor: Alan Sommerer, Warthman Associates
Managing Editor: Forrest Warthman, Warthman Associates

Review Comments and/or Code Examples:

Steve Barnett, Absoft Corporation
Bob Blainey, IBM Toronto Laboratory
Patrick Bohrer, IBM Microelectronics Division
Gary Davidian, Power Computing Corporation
Kaivalya Dixit, IBM RISC System/6000 Division
Bill Hay, IBM Toronto Laboratory
Richard Hooker, IBM Microelectronics Division
Steve Hoxey, IBM Toronto Laboratory
Steve Jasik, Jasik Designs
Faraydon Karim, IBM Microelectronics Division
Lena Lau, IBM Toronto Laboratory
Cathy May, IBM Thomas J. Watson Research Center
John McEnerney, Metrowerks, Inc.
Dave Murrell, IBM Microelectronics Division
Tim Olson, Apple Computer, Inc.
Brett Olsson, IBM System Technology and Architecture Division
Tom Pennello, MetaWare, Inc.
Mike Peters, IBM PowerPC Performance Group
Brian Peterson, IBM Microelectronics Division
Nam H. Pham, IBM Microelectronics Division
Warren Ristow, Apogee Software, Inc.
Alex Rosenberg, Apple Computer, Inc.
Tim Saunders, IBM Microelectronics Division
Ed Silha, IBM System Technology and Architecture Division
Fred Strietelmeier, IBM System Technology and Architecture Division
S. Surya, IBM PowerPC Performance Group
Maureen Teodorovich, IBM Microelectronics Division
Hank Warren, IBM Thomas J. Watson Research Center
Pete Wilson, Groupe Bull

Notation

0:31
Bits 0 through 31 of a big-endian word.

Ra
General-purpose register a, where a is a number or letter other than A.

RA
General-purpose register indicated by the field 11:15 in the instruction encoding for load/store instructions that do not update and addi and addis instructions. If this field indicates R0, the value 0 is used.

FRa_0:36
Floating-point register a, big-endian bits 0:36.

crn
Condition Register field n.

crn[lt]
The lt bit in Condition Register field n. The following table summarizes the names of the bits in the Condition Register fields used in this book.

Condition Register Field Bits Bit Name Bit Position in Field Description lt 0 The result of a recording fixed-point operation or a fixed-point compare. gt 1 eq 2 so 3 fx 0 in CR1 The result of a recording floating-point operation. fex 1 in CR1 vx 2 in CR1 ox 3 in CR1 fl 0 The result of a floating-point compare operation. fg 1 fe 2 fu 3 (x)
The contents of x, where x indicates some register or field.

(RA|0)
The contents of general-purpose register A, or the value 0 if RA indicates R0.

0xFFFF
Decimal 65535 (64K) in hexadecimal notation.

0b0011
Decimal 3 in binary notation.

x || y
The concatenation of x and y.

ⁿx
x repeated n times.

Is a member of.

¬
Logical NOT.

Logical equivalence.

instruction
A PowerPC instruction mnemonic.

[.]
An optional period at the end of a PowerPC instruction mnemonic. It causes condition codes for the result to be stored in the Condition Register (CR).

[o]
An optional "o" at the end of a PowerPC instruction mnemonic. It causes the SO (summary overflow) and OV (overflow) bits of the fixed-point exception register (XER) to reflect the result.

Acronyms, words, and phrases are defined in the Glossary at the back of the book. The following table gives the equivalent mnemonic for extended mnemonics used in this book:

Extended Mnemonics Used in This Book Extended Mnemonic Equivalent Mnemonic Name bctr bcctr 20,bi Branch Unconditionally to CTR bctrl bcctrl 20,bi Branch Unconditionally to CTR Setting LR bdnz target bc 16,bi,target Decrement CTR, Branch If CTR 0 bdnzf target bc 8,bi,target Decrement CTR, Branch If CTR 0 and Condition False bdz target bc 18,bi,target Decrement CTR, Branch If CTR = 0 beq crn,target bc 12,4*n+2,target Branch If Equal To bf crn[xx],target bc 4,bi,target Branch If Condition False bge crn,target bc 4,4*n,target Branch If Greater Than Or Equal To bgt crn,target bc 12,4*n+1,target Branch If Greater Than bgtlr crn bclr 12,4*n+1 Branch If Greater Than to LR ble crn, target bc 4,4*n+1,target Branch If Less Than Or Equal To blr bclr 20,bi Branch Unconditionally to LR blt crn,target bc 12,4*n,target Branch If Less Than bne crn,target bc 4,4*n+2,target Branch If Not Equal To bt crn[xx],target bc 12,bi,target Branch If True cmplw crn,Ra,Rb cmpl crn,0,Ra,Rb Compare Logical Word cmplwi crn,Ra,UI cmpli crn,0,Ra,UI Compare Logical Word Immediate cmpw crn,Ra,Rb cmp crn,0,Ra,Rb Compare Word cmpwi crn,Ra,SI cmpi crn,0,Ra,SI Compare Word Immediate li Rx,value addi Rx,0,value Load Immediate lis Rx,value addis Rx,0,value Load Immediate Shifted mfctr Rx mfspr Rx,9 Move From CTR mflr Rx mfspr Rx,8 Move From LR mfxer Rx mfspr Rx,1 Move From XER mr Rx,Ry or Rx,Ry,Ry (ori Rx,Ry,0) Move Register mtctr Rx mtspr 9,Rx Move To CTR mtlr Rx mtspr 8,Rx Move To LR mtxer Rx mtspr 1,Rx Move To XER not Rx,Ry nor Rx,Ry,Ry Logical NOT slwi Rx,Ry,n rlwinm Rx,Ry,n,0,31-n Shift Left Immediate srwi Rx,Ry,n rlwinm Rx,Ry,32-n,n,31 Shift Right Immediate sub Rx,Ry,Rz subf Rx,Rz,Ry Subtract subi Rx,Ry,value addi Rx,Ry,-value Subtract Immediate LR—Link Register CTR—Count Register crn—Condition Register field n xx—Alphabetic code for bit in Condition Register field (see previous table) UI—Unsigned 14-bit intermediate SI—Signed 14-bit intermediate bi—Bit in Condition Register[ Table of Contents | Index ]