Appendix E

E. Glossary

This glossary defines terms used in this book. Italicized terms within definitions are themselves defined elsewhere in the glossary. The terms are defined with respect to a 32-bit PowerPC implementation. For more information on the terms defined here, see the Index at the end of the book.

AA
Bit 30 of certain branch instructions. It differentiates between relative (displacement from current instruction address) and absolute addressing modes.

ABI
Application Binary Interface.

activation record
A block of storage in the run-time stack used to hold information for a procedure.

address
A 32-bit or 64-bit effective address generated by a program.

algebraic
A type of load instruction that places the sign-extended memory value in the destination register.

alias
The relationship between two data entities or a data entity and a pointer that denote a single area in memory.

alignment
The positioning in memory of operand values at addresses relative to their size or length. Thus, a properly aligned value is positioned at an address equal to an integral multiple of its size.

antidependence
A type of name dependence for which the instruction's destination register or memory location is the preceding instruction's source register or memory location. Compare write after read.

API
Application Program Interface.

argument
A parameter passed between a calling procedure and the called procedure.

atomic
Performed as a single indivisible unit, without interference or interruption.

B
Bytes.

b
Bits.

base
A value in a register that is added to an immediate value or to the value in an index register to form the effective address for a load or store instruction.

base address
The reference address of a data structure in memory. Parts of the data structure are accessed relative to this address.

basic block
Single-entry, single-exit unit of program code with no internal branch targets.

big-endian
An ordering of bytes and bits in which the lowest-address byte and lowest-numbered bit are the most-significant (high) byte and bit, respectively. Compare endian orientation and little-endian.

Big-Endian mode
When the Little-Endian (LE) bit in the Machine State Register is clear, the processor is said to run in Big-Endian mode. This mode handles data as if it were big-endian. Compare Little-Endian mode.

binary point
A radix point in the binary representation of a floating-point number.

Block Address Translation (BAT)
A hardware mechanism in which effective addresses are translated directly to real addresses, bypassing the segmentation and paging mechanisms. The BAT mechanism is typically used to store large numeric arrays, display buffers or other large data structures, and it has higher priority than segmented address translations. Compare Segmented Address Translation.

blocking
An optimization that transforms a loop nest into an iteration over blocks that are designed to improve the locality of memory access for better use of the cache and TLB.

branch
An instruction that conditionally or unconditionally transfers control.

branch-and-link
A branch instruction that writes the current instruction address plus 4 into the Link Register.

branch folding
The execution of a resolved or correctly predicted branch instruction in parallel with other instructions so as to prevent a stall due to a control transfer in the non-branch pipelines.

branch-on-count
A conditional branch instruction that has bit 2 of the BO field cleared. These instructions decrement the Count Register and test it for zero.

branch prediction
Selecting an outcome for an unresolved conditional branch so that execution can continue. Misprediction requires the processor to back up, cancel instructions executed subsequent to the branch, and begin execution along the correct direction (taken or not taken).

Branch-Processing Unit
A logic block that executes control transfer instructions and, in some implementations and in the Common Model, the Condition Register logical instructions.

branch resolution
The correct determination of the direction (taken or not taken) of a conditional branch instruction.

branch target address cache
A cache used in branch prediction. It stores the target addresses of taken branches as a function of the branch address. When the branch instruction is fetched, the fetch unit will fetch the target address on the next cycle unless a fetch address of higher priority exists.

BTAC
See branch target address cache.

bubble
An unused stage in the pipeline during a cycle. Compare stall.

bypass
See forward.

CA
See Carry bit.

cache block
An aligned unit of storage operated on by a cache management instruction. The maximum block size is one page.

cache hit
A cache access for which the cache block is valid.

cache miss
A cache access in which the cache block is either not present or not valid.

cache touch
Compiler-directed method of prefetch in which the processor is informed of cache blocks that will be required in the near future. If the processor has available cycles on the bus, it may load the requested blocks so that the subsequent accesses hit in the cache.

Carry bit
Bit 2 in the Fixed-Point Exception Register (XER). Fixed-point carrying and extended arithmetic instructions set CA if there is a carry out of the most-significant bit. Shift Right Algebraic instructions set CA if any 1-bits are shifted out of a negative operand.

CIA
Current Instruction Address.

clean-up code
In loops that have been unrolled or blocked, an additional code sequence that ensures that all iterations of the original code are executed in the unrolled or blocked code.

clear
To write a zero (0) in a bit location. Compare set.

coherence
The ordering of writes to a single location, such as shared memory. Atomic stores to a given location are coherent if they are serialized in some order, and no processor is able to observe any subset of those stores as occurring in a conflicting order.

coherence block
The block size used in managing memory coherence.

committed
With respect to an instruction, when the process writing back its result has begun and cannot be prevented by an exception. Compare write back.

Common Model
A fictional PowerPC implementation whose resources and timing represent a compiler target when scheduling code that is expected to perform well on all PowerPC implementations.

compiler
A program that translates a source program into machine language output in an object module.

complete
With respect to an instruction, when its result is both available to another instruction and can be retired, and it is past the point where the it can cause an exception. Compare retire.

completion unit
In some implementations, a buffer where instructions reside following the finish of execution until the program-order write back of the results.

condition code
The properties of operation results, as reflected in bit settings in status registers. The Condition Register has eight 4-bit condition code fields. Compare Condition Register.

Condition Register
The 32-bit register that indicates the outcome of certain operations and provides a means for testing them as branch conditions.

context
The privilege, protection and address-translation environment of instruction execution.

context switch
A process or task switch.

context synchronization
The halting of instruction dispatch from the fetch buffer, clearing of the fetch buffer, and completion of all instructions currently in execution (i.e., past the point where they can produce an exception) in the context in which they began execution. The first instruction after a context-synchronizing event is fetched and executed in the context established by that instruction. Context synchronization occurs when certain instructions are executed (such as isync or rfi) or when certain events occur (such as an exception). All context-synchronizing events are also execution-synchronizing. Compare execution synchronization.

control dependence
The relationship of an instruction with a branch instruction that requires them to execute in program order.

control hazard
A situation in which a control dependence occurs in the instruction sequence, so the processor could generate a result inconsistent with execution in program order.

Count Register
The 32- or 64-bit register that holds a loop count, which can be decremented during certain branch instructions, or provides the branch target address for the bcctr[l] instructions.

CPU time
The time required to complete an instruction sequence. It is equal to the (cycle time) * (number of instructions) * (cycles per instruction).

CR
See Condition Register.

CRn
One of eight 4-bit fields (n = 0,...,7) in the Condition Register (CR) that reflect the results of certain operations.

CTR
See Count Register.

cycle
The internal processor clock cycle.

data dependence
The relationship of a given instruction with a preceding instruction in which an input for the given instruction is the result of the preceding instruction. This result may be an indirect input through a data dependence on one or more intermediate instructions. Also known as a flow dependence, a true dependence, or a def-use dependence.

data hazard
A situation in which an instruction has a data dependence or a name dependence on a prior instruction, and they occur close enough together in the instruction sequence that the processor could generate a result inconsistent with execution in program order.

dedicated register
A register designated by an ABI for a specific use.

def-def dependence
See output dependence.

def-use dependence
See data dependence.

denormal
See denormalized number.

denormalized number
A nonzero floating-point number whose exponent is the format's minimum, but represented as all zeros, and whose implicit leading significand bit is zero.

dependence
A relationship between two instructions that requires them to execute in program order. Dependence is a property of a program. See control dependence, data dependence, and name dependence.

direct-store segment
A memory segment, typically used for I/O, in which effective addresses are mapped onto an external address space, usually an I/O bus.

displacement
An offset or index from a base address.

double-precision format
An IEEE 754 floating-point data type. The common 64-bit implementation includes a 52-bit significand, an 11-bit biased exponent, an implicit binary point, and a 1-bit sign. Also called double format.

doubleword
8 bytes.

dynamic branch prediction
Methods in which hardware records the resolution of branches and uses this information to predict the resolution of a branch when it is encountered again.

dynamic linking
Linking of a program in which library procedures are not incorporated into the load module, but are dynamically loaded from their library each time the program is loaded.

dynamic store forwarding
A feature of the PowerPC 601 processor that allows the floating-point to collapse a floating-point arithmetic operation followed by a floating-point store operation that depends on the result of the arithmetic operation into a single operation through the pipeline.

endian orientation
A view of bits and bytes in which either the little end (least-significant or low end) or the big end (most-significant or high end) is assigned the lowest value or address. Thus, there are two types of endian orientation—little-endian and big-endian. Endian orientation applies to bits, in the context of register-value interpretation, and to bytes, in the context of memory accesses. See Danny Cohen[1981]. Compare low and high.

exception
An error, unusual condition, or external signal that may alter a status bit and will cause a corresponding interrupt, if the interrupt is enabled.

execution synchronization
The halting of instruction dispatch and the completion of all instructions currently in execution (i.e., past the point where they can produce an exception) in the context in which they began execution. Unlike context synchronization, the fetch buffer is not cleared and the execution-synchronizing event need not be executed in a context established by that event (it can be executed in the context of prior instructions). Compare context synchronization.

execution time
The number of cycles that an instruction occupies an execution unit preventing another independent instruction from being issued to the same unit. The execution time is normally equal to the length of the longest execution stage in cycles.

exponent
The component of a binary floating-point number that signifies the integer power of two by which the significand is multiplied in determining the value of the represented number. Occasionally the exponent is called the signed or unbiased exponent.

extended mnemonic
A simplified instruction mnemonic defined (and required) by the PowerPC architecture.

external cache
Optional cache external to the processor, often called level-2 (L2) cache.

fall-through path
The path of execution following a not-taken conditional branch.

FE0, FE1
See Floating-Point Exception Mode bits.

fetch
To load instructions (as opposed to data) from storage. Compare read.

FEX
See Floating-Point Enabled Exception Summary bit.

FI
See Floating-Point Fraction Inexact bit.

first-class value
A value for which the architecture explicitly supports operations.

fixed-point
The PowerPC architecture's term for integer. Compare floating-point.

Fixed-Point Exception Register
The 32-bit register whose bits reflect the outcome of certain fixed-point operations.

Fixed-Point Unit
A logic block that executes integer arithmetic and logical instructions and, in some implementations and in the Common Model, loads and stores.

flat memory
Memory in which all segments overlap the same linear address range.

floating-point
A fixed-length binary form of the familiar scientific notation, in which a real number is represented by a pair of numerals. The real number is the product of one of the numerals (a fixed-point part called the significand), and a value obtained by raising the implicit base to a power denoted by the other numeral (called the exponent). Compare integer.

Floating-Point Available bit
Bit 18 (FP) in the Machine State Register. It controls access to and execution of floating-point instructions.

Floating-Point Enabled Exception Summary bit
Bit 1 (FEX) in the Floating-Point Status and Control Register (FPSCR), and in field 1 of the Condition Register (CR1). It indicates that an enabled exception bit is currently set.

Floating-Point Exception Mode bits
Bit 20 (FE0) and bit 23 (FE1) in the Machine State Register. They specify the enabling, recoverability and precision of interrupts caused by floating-point instructions.

Floating-Point Exception Summary bit
Bit 0 (FX) in the Floating-Point Status and Control Register (FPSCR) and in field 1 of the Condition Register. It indicates that an exception bit in the FPSCR has changed from 0 to 1.

Floating-point Fraction Inexact bit
Bit 14 (FI) in the Floating-Point Status and Control Register (FPSCR). It indicates that an instruction either produced an inexact significand during rounding or caused a disabled overflow exception. This bit is a non-sticky version of the XX bit in the FPSCR register.

Floating-Point Fraction Rounded bit
Bit 13 (FR) in the Floating-Point Status and Control Register (FPSCR). It indicates that the instruction that rounded the intermediate result incremented the fraction.

Floating-Point Inexact Exception bit
Bit 6 (XX) in the Floating-Point Status and Control Register (FPSCR). It indicates that an Inexact exception has occurred. This is a sticky version of the FI bit in the FPSCR register.

Floating-Point Inexact Exception Enable bit
Bit 28 (XE) in the Floating-Point Status and Control Register (FPSCR). It causes the processor to generate a Program interrupt when an Inexact exception occurs.

Floating-Point Invalid Operation Exception Enable bit
Bit 24 (VE) in the Floating-Point Status and Control Register (FPSCR). It causes the processor to generate a Program interrupt when an Invalid Operation exception occurs.

Floating-Point Invalid Operation Exception (0 ÷ 0) bit
Bit 10 (VXZDZ) in the Floating-Point Status and Control Register (FPSCR). It indicates that a division of zero by zero has occurred.

Floating-Point Invalid Operation Exception ( ÷ ) bit
Bit 9 (VXIDI) in the Floating-Point Status and Control Register (FPSCR). It indicates that a division of infinity by infinity has occurred.

Floating-Point Invalid Operation Exception ( - ) bit
Bit 8 (VXISI) in the Floating-Point Status and Control Register (FPSCR). It indicates that a magnitude subtraction of infinities has occurred.

Floating-Point Invalid Operation Exception ( × 0) bit
Bit 11 (VXIMZ) in the Floating-Point Status and Control Register (FPSCR). It indicates that a multiplication of infinity by zero has occurred.

Floating-Point Invalid Operation Exception (Invalid Compare) bit
Bit 12 (VXVC) in the Floating-Point Status and Control Register (FPSCR). It indicates that an ordered comparison involving a NaN has occurred.

Floating-Point Invalid Operation Exception (Invalid Integer Convert) bit
Bit 23 (VXCVI) in the Floating-Point Status and Control Register (FPSCR). It indicates that the result of a floating-point-to-integer conversion is invalid.

Floating-Point Invalid Operation Exception (Invalid Square Root) bit
Bit 22 (VXSQRT) in the Floating-Point Status and Control Register (FPSCR). It indicates that an invalid square root exception has occurred.

Floating-Point Invalid Operation Exception (SNaN) bit
Bit 7 (VXSNAN) in the Floating-Point Status and Control Register (FPSCR). It indicates that a signaling NaN was an input operand to a floating-point operation.

Floating-Point Invalid Operation Exception (Software Request) bit
Bit 21 (VXSOFT) in the Floating-Point Status and Control Register (FPSCR). It indicates that an mcrfs, mtfsfi, mtfsf, mtfsb0 or mtfsb1 instruction was executed setting VXSOFT in order to generate an exception.

Floating-Point Invalid Operation Exception Summary bit
Bit 2 (VX) in the Floating-Point Status and Control Register (FPSCR) and bit 2 in field 1 of the Condition Register (CR1). It indicates that an Invalid Operation Exception bit is set.

Floating-Point Non-IEEE mode bit
Bit 29 (NI) in the Floating-Point Status and Control Register (FPSCR). Setting the bit enables Non-IEEE mode. See Non-IEEE mode.

Floating-Point Overflow Exception bit
Bit 3 (OX) in the Floating-Point Status and Control Register (FPSCR), and in field 1 of the Condition Register (CR1). It indicates that a floating-point Overflow exception has occurred.

Floating-Point Overflow Exception Enable bit
Bit 25 (OE) in the Floating-Point Status and Control Register (FPSCR). It causes the processor to generate a Program interrupt when an Overflow exception occurs.

Floating-Point Register
One of the 32 64-bit registers that are used for the source and destination operands in floating-point arithmetic operations.

Floating-Point Result Flags
The field located at 15:19 in the Floating-Point Status and Control Register (FPSCR), which includes the Floating-Point Result Class Descriptor (C, bit 15) and the Floating-point Condition Code (FPCC, bits 16:19). Various combinations of the flags identify a result as a positive or negative normalized, denormalized, zero or infinite number, or a quiet NaN.

Floating-Point Rounding Control
Bits 30:31 (RN) in the Floating-Point Status and Control Register (FPSCR). They specify the processor's rounding mode (Round to Nearest, Round toward 0, Round toward + , or Round toward - ).

Floating-Point Status and Control Register
The 32-bit register that controls the handling of floating-point exceptions and records status resulting from floating point operations.

Floating-Point Underflow Exception bit
Bit 4 (UX) in the Floating-Point Status and Control Register (FPSCR). It indicates that an Underflow exception has occurred.

Floating-Point Underflow Exception Enable
Bit 26 (UE) in the Floating-Point Status and Control Register (FPSCR). It causes the processor to generate a Program interrupt when an Underflow exception occurs.

Floating-Point Unit
A logic block that executes floating-point arithmetic, conversion, rounding instructions.

floating-point value
A fractional number determined by the signed product of a significand and base raised to the power of a signed exponent. Also called a real number.

Floating-Point Zero Divide Exception bit
Bit 5 (ZX) in the Floating-Point Status and Control Register (FPSCR). It indicates that a Zero-Divide exception has occurred.

Floating-Point Zero-Divide Exception Enable bit
Bit 27 (ZE) in the Floating-Point Status and Control Register (FPSCR). It causes the processor to generate a Program interrupt when a Zero-Divide exception occurs.

forward
To immediately provide the result of the previous instruction to the current instruction, at the same time that the result is written to the register file. Also called bypass.

FP
See Floating-Point Available bit.

FPRF
See Floating-Point Result Flags.

FPR0:31
The 32 64-bit Floating-Point Registers. They are used for source and destination operands in floating-point operations.

FPSCR
See Floating-Point Status and Control Register.

FPU
Floating-Point Unit.

FR
See Floating-Point Fraction Rounded bit.

fraction
The 23- or 52-bit field of a significand that lies to the right of its implied binary point.

FRx
A Floating-Point Register, where "x" is any number or letter.

function
A procedure that returns a value.

functional class
One of the divisions of the PowerPC architectural resources: branch, fixed-point, and floating-point. This separation simplifies superscalar operation.

FX
See Floating-Point Exception Summary bit.

General-Purpose Register
Any of the 32 registers used for integer, logical, comparison, load, and store operations.

halfword
2 bytes.

hazard
A situation in which the overlapped or out-of-order execution of a pair of instructions could generate a result inconsistent with execution of the instructions in program order. A hazard is a property of a program running on a specific implementation. See control hazard, data hazard, and structural hazard. Compare dependence.

high
The most-significant bit or byte numbers in a field, register or memory. Compare low.

hoist
To move an instruction to an earlier point in the program execution order.

home location
The storage location, typically in the local stack frame of the called procedure, reserved for an actual parameter that has been passed in a register.

IEEE 754
The IEEE Standard for Binary Floating-Point Arithmetic 754-1985.

IEEE mode
The operating mode in which floating-point operations generally conform to IEEE 754. The mode is enabled by clearing the NI bit (bit 29) of the FPSCR. Compare Non-IEEE mode.

immediate operand
An operand included in an instruction. Also called immediate constant or immediate value.

implicit bit
An implied value of 1 or 0 located immediately to the left of an implied binary point in the significand of single- and double-precision floating-point data types.

imprecise
A non-restartable event occurring at a point other than an instruction boundary. Compare precise.

imprecise interrupt
An instruction-caused interrupt in which the pipeline state, including intermediate data of partially executed instructions, is frozen and saved. Imprecise interrupts occur one or more instructions after execution of the instruction causing the interrupt. They are not restartable. The PowerPC architecture defines one imprecise interrupt: the imprecise-mode floating-point enabled exception. Compare precise interrupt.

index
An offset from a base address.

indirect
An access is said to be "indirect" when a register holds its target. For example, an indirect branch is one whose target is specified in a register.

Inexact exception
A floating-point exception, defined by the IEEE 754 standard, that is generated when the result of a calculation is not exact. Most programs mask this exception by having XE = 0.

inline expansion
An optimization in which the reference to a procedure is replaced with the code of the procedure itself to eliminate calling overhead.

instruction queue
A holding place for fetched instructions that are awaiting decode.

instruction restart
The re-execution of an instruction that has generated an exception.

integer bit position
The first bit-position in the significand to the left of the binary point in a floating-point data-type format.

interlock
A hardware mechanism that enforces program-order execution of operations under certain dependency circumstances.

interprocedural analysis
The process of inspecting referenced procedures for information on relationships between arguments, returned values, and global data.

interrupt
A change in the machine state in response to an exception.

K
2¹⁰ (as in KB for 1,024 bytes).

latch point
The branch in an iterative construct that transfers control from the bottom of the loop back to the top. Also known as the back edge of the flow graph.

latency
The number of cycles required to complete an instruction. Compare throughput.

LE
See Little-Endian Mode bit.

least-significant
The bits or bytes having the least weight in the number representation.

lifetime analysis
The process of inspecting references to variables to determine whether the final assignment to a variable needs to be stored or can be discarded.

Link Register
The 32- or 64-bit register used to provide the branch target address for the bclr instruction and to hold the return address after the bl instruction.

linkage convention
A set of conventions that determines how control transfers to other procedures occur. Also called calling conventions. Compare run-time environment.

linkage editor
A program that resolves cross-references between separately compiled or assembled object modules and then assigns final addresses to create a single relocatable load module. If a single object module is linked, the linkage editor simply makes it relocatable. Also known as the linker.

little-endian
An ordering of bytes and bits in which the lowest-address byte and lowest-numbered bit are the least-significant (low) byte and bit, respectively. Compare endian orientation, big-endian, low and high.

Little-Endian Mode bit
Bit 31 (LE) in the Machine State Register. It specifies the current operating mode as Little-Endian (LE = 1) or Big-Endian (LE = 0).

LK
Bit 31 of certain branch instructions. When set to 1, it causes the Link Register (LR) to be loaded with the current instruction address plus 4.

load
To read data (but not instructions) from storage. Compare fetch.

loader
A program that reads the load module into memory, performing all necessary dynamic linking, so that the module can execute.

load-following-store contention
In implementations that can dynamically reorder the execution of memory-accessing instructions, a situation in which the reordering could violate program semantics because a reordered load is executed prior to a store that modifies an overlapping area in memory. PowerPC processors automatically maintain correct program behavior, but this situation degrades performance.

load module
The executable output file produced by the linkage editor.

load-store bound
Where the delay in a series of computations is caused by the amount of data that must be loaded into registers or stored back into memory.

load and store queues
On some implementations, buffers that are used to hold pending memory accesses.

Load-Store Unit
In some implementations, a logic block that executes memory accessing instructions.

load-use delay
The time between when a value is requested from cache or memory and when it is available to a subsequent instruction.

locality
See spatial locality and temporal locality.

local variable
A symbol defined in one program module or procedure that can be used only in that program module or procedure.

loop fusion
An optimization that takes the bodies of loops with identical iteration counts and combines them into a single loop.

loop interchange
An optimization that changes the order of loops within a loop nest to achieve stride minimization or to eliminate data dependencies.

loop unrolling
A transformation of a loop that copies the loop body a specified number of times and adjusts the loop control appropriately. The resulting larger loop body minimizes the loop control overhead and presents improved opportunities for other optimizations.

low
The least-significant bit or byte numbers in a field, register or memory. Compare high. Also, the highest-numbered bits or bytes in a data structure.

LR
See Link Register.

LSB
Least-significant (low) byte.

lsb
Least-significant (low) bit.

machine-dependent optimization
A code-improving transformation for a particular implementation, architecture or ABI.

machine-independent optimization
A code-improving transformation that does not depend on the implementation, architecture, or ABI.

Machine State Register
A 32- or 64-bit register that defines certain states of the processor.

mask
A pattern of bits used to keep, delete, or test another pattern of bits.

memory
Unless otherwise stated, main (virtual) memory. The term is not normally used for cache, ROM or other memory structures without specific qualification.

memory coherence
See coherence.

misaligned
Not in alignment.

miss penalty
The time required to fill a cache block after a cache miss. Also, for loads, the additional latency due to a cache miss as compared to a cache hit.

MMU
Memory management unit, which controls address translation and protection.

most-significant
The bits or bytes having greatest weight in the number representation.

MSB
Most-significant (high) byte.

msb
Most-significant (high) bit.

MSR
See Machine State Register.

name dependence
The relationship between two instructions that, although not data dependent, both access a particular register or memory location as an operand, so they must be executed in program order. If the register or memory location for one of the instructions is changed either statically by the compiler or dynamically by the processor, the name dependence is removed. See antidependence and output dependence.

NaN
An abbreviation for Not a Number; a symbolic entity encoded in floating-point format. See signaling NaN and quiet NaN.

NI
See Floating-Point Non-IEEE-Mode Enable bit.

NIA
Next Instruction Address. For taken branch instructions, it is the branch target address. For instructions that do not branch or otherwise cause non-sequential instruction fetching, it is the current instruction address (CIA) plus 4 bytes.

Non-IEEE mode
An implementation-dependent floating-point mode in which the processor produces some floating-point results that do not conform with IEEE 754. Trapping is suppressed by forcing arithmetically reasonable values, rather than trapping to produce IEEE-specified results, such as using zeros for denormalized values. Non-IEEE mode makes performance deterministic, which is critical for certain applications. See Floating-Point Non-IEEE Enable Mode bit.

non-volatile register
A register designated by an ABI whose value must be preserved across procedure calls. Also called a callee-save register.

no-op
No-operation. A single-cycle operation that does not affect registers or generate bus activity.

normal
See normalized number.

normalize
To shift the intermediate result's significand to the left while decrementing the exponent for each bit shifted until the most significant bit is a 1.

normalized number
A nonzero floating-point number whose leading implicit significand bit is 1 and whose exponent bits are not all 1s, nor all 0s.

object module
The output file of a compiler or other language translator. It includes the machine language translation and other information for symbolic binding and relocation.

OE
See Floating-Point Overflow Exception Enable bit.

offset
A value that is added to a base address.

optimization
The process of achieving improved run-time performance or reduced code size of an application. Optimization can be performed by a compiler, by a preprocessor, or through hand-tuning of the source code or the assembly language output of a compiler.

ordinary segment
A general-use segment in memory or memory-mapped I/O that can hold references to code and data, or a mixture thereof. There can be up to 16M such segments. Each segment is exactly 256MB in size and the segments may not overlap.

out-of-order
Not in program order. Out-of-order applies to instruction processing stages, but the final write back stage must be in program order.

output dependence
A type of name dependence for which the instruction's destination register or memory location is the preceding instruction's destination register or memory location. Compare Write After Write.

OV
See Overflow bit.

overflow
A signed integer arithmetic error in which the result cannot be represented in the destination register. An floating-point arithmetic error in which the exponent of the result exceeds the largest exponent representable in the destination format.

Overflow bit
Bit 1 (OV) in the Fixed-Point Exception Register (XER). It indicates an overflow result.

OX
See Floating-Point Overflow Exception bit.

page
A 4KB storage unit aligned on a 4KB boundary. Each page can have independent protection and control attributes, and change and reference status can be independently recorded.

path length
The number of instructions in an instruction sequence. See CPU time.

pipeline
The sequence of stages in instruction processing. For each instruction passing through the pipeline, some stages are skipped and some are repeated. Pipelining makes it possible to overlap instruction processing so that throughput (the number of instructions completed per cycle) is greater than latency (the number of cycles required to complete an instruction).

pointer
In the many programming languages, a variable that contains the address of another variable.

pointer chasing
Processing a series of pointers to other pointers in a computer program.

POWER
Performance Optimized With Enhanced RISC, the predecessor architecture on which the PowerPC architecture is based. The POWER architecture is used in RS/6000 systems.

PR
The problem state bit in the Machine State Register (bit 17). In page translation, the PR bit is used in conjunction with the PP, N, Ks and Kp bits to determine access privilege. In the PowerPC architecture, the user (non-privileged) mode is called the problem state. Compare supervisor state.

precise
A restartable event occurring at an instruction boundary. Compare precise interrupt.

precise interrupt
An instruction-caused interrupt in which dispatching of new instructions to the pipeline is halted, instructions currently in the pipeline are completed to the extent possible, and the state of the processor is changed so as to match the sequential order of execution. Instructions following the one causing the interrupt can be restarted. Compare imprecise interrupt.

precision
The number of bits in the significand of a floating-point data format.

predicate
A logical relationship.

prefetch
To fetch instructions ahead of the processor's ability to dispatch them.

preprocessor
A program that modifies, and possibly optimizes, source programs before they are processed by a compiler.

privilege level
One of two access-permission levels: supervisor (PR=0) or problem (PR=1). See PR.

privilege mechanism
A resource-protection mechanism controlled by operating-system parameters in the Segment Registers, page table entries and Machine State Register.

privileged instruction
An instruction that can be executed only in the supervisor state. See privilege level.

problem state
The less privileged of the processor's two operating states (the other is supervisor state, which is the more privileged state). Problem state is enabled when the problem state (PR) bit in the Machine State Register is 1. In problem state, software cannot access most control registers or the supervisor memory space, and cannot execute privileged operations.

procedure
A subprogram invoked by a branch-and-link instruction. Procedures, unlike tasks, can be re-entrant because each call (entrance) pushes processor state and parameters onto the stack, allowing nested returns. Compare task, process and thread.

process
A unit of resource ownership created and managed by the operating system. Processes correspond to user jobs or applications. They own resources such as memory segments, open files and threads. Unlike the threads that can be created within a process, a process is not itself dispatched for execution. Also called task. Compare thread and procedure.

processor starvation
A situation in which an execution unit or processor is stalled waiting for operand data. Compare stall.

profile
To collect information from an executing program that can be fed back into a compiler to improve performance. Profiling is often used to improve branch prediction.

program order
The order in which instructions occur for execution in the program. When some instruction sequence executes in program order, the processing of one instruction appears to complete before the processing of the next instruction appears to begin. Pipelined and superscalar processors attempt to maintain the appearance of execution in program order. Compare sequential order.

protection
The mechanisms, implemented by means of privilege levels or states, that limit software access to other software and hardware resources.

quadword
16 bytes.

quiet NaN
A floating-point Not a Number (NaN) that propagates through every arithmetic operation, except ordered comparisons, without signaling exceptions. It is used to represent the results of certain invalid operations, such as some arithmetic operations involving infinities or NaNs. In the PowerPC architecture, a quiet NaN is denoted by its most significant fraction bit being 1 and all of its exponent bits being 1. Compare signaling NaN.

R0:32
Any of the 32 General-Purpose Registers. They are used for integer, logical, and string operations.

RAW
See read after write.

Rc
See record.

read
To load data (as opposed to instructions) from storage. Compare fetch.

read after write
A data hazard in which an instruction attempts to read a source operand before a prior instruction has written it, causing the instruction to read an incorrect value. Compare data dependence.

record
To set or clear bits in the Condition Register (CR) to reflect characteristics of an executed instruction's result. The recording is caused by instruction mnemonics that end in a period (.); such instructions have the Rc bit (bit 31) of the instruction set to 1.

re-entrant
The ability of a program to be executed simultaneously by two or more processes or threads.

register allocation
The process of selecting which variables will reside in registers at any point in the program.

rename register
In some implementations, an additional register that, along with some control logic, permits the elimination of a WAW or WAR hazard.

reservation
An exclusive right to access a storage location. Reservations are set with the lwarx instruction and cleared with the stwcx. instruction and other instructions that store into the reservation granule in which the reservation is set. Compare reservation granule.

reservation granule
The storage block size corresponding to the number of low-order bits ignored when a store to a real address is compared with a reservation at that address.

reservation station
In some implementations, an instruction buffer associated with an execution unit that holds issued instructions until the execution unit and required source operands are ready. The reservation station allows subsequent instructions to issue and execute in other execution units even though a prior instruction is stalled.

resolved
Describes a branch whose condition and target address are known.

restart
See instruction restart.

retire
To write the results of a completed instruction back to memory. An instruction can be retired after it completes. Compare complete.

RN
See Floating-Point Rounding Control Field.

run-time environment
A set of conventions that determines how instructions and data are loaded into memory, how they are addressed, and how functions and system services are called (linkage or calling conventions). To obtain usable code, a compiler and its target operating system must observe the same run-time environment model.

Rx
A General-Purpose Register, where "x" is any number or letter.

scheduling
A compiler optimization that reorders the instruction sequence subject to data and control flow restrictions so as to maximize use of the processor's hardware.

segment
A fixed 256-MB unit of address space that can hold code, data, or any mixture thereof. The PowerPC architecture specifies two types of segments, ordinary and direct-store (for POWER architecture compatibility). In 32-bit implementations, up to sixteen segment registers can be loaded with entries that select segments. The 52-bit virtual address space supports up to 16M fixed-length (256MB), non-overlapping segments.

sequential execution model
The model of program execution in which each instruction appears to complete before the next instruction starts.

sequential order
The order in which the compiler output of a program appears in storage. Compare program order.

serialization
A implementation-dependent, hardware-enforced alteration of the processor state so as to match the sequential ordering of instructions. The types of serialization are Compare synchronization. See also sequential order, program order, context synchronization, and execution synchronization.

set
To write a value of one (1) into a bit location. Compare clear.

SF
See Sixty-Four-Bit Mode bit.

shadow register
A register that can be updated by instructions that are executed out-of-order without destroying machine state information.

sign extension
The filling of an operand into a wider register or format in which the additional bits are copied from the sign bit. Compare zero extension.

signaling NaN
A floating-point Not a Number (NaN) that causes an invalid-operation exception when used. In the PowerPC architecture, a signaling NaN is denoted by its most significant fraction bit being 0 and all of its exponent bits being 1. Compare quiet NaN.

significand
The component of a binary floating-point number that consists of an implicit leading bit to the left of its implied binary point and a fraction field to the right.

single-precision format
The narrowest precision IEEE 754 floating point data type. The common 32-bit floating-point data type that includes a 23-bit fraction, an 8-bit biased exponent, and a sign bit. Also called single format.

Sixty-Four-Bit Mode bit
The bit (bit 0) in the Machine State Register that specifies whether the processor runs in 32- or 64-bit mode on 64-bit implementations.

SNaN
See signaling NaN.

SO
See Summary Overflow bit.

software pipelining
A loop optimization in which the body of the loop in divided into a series of stages that are executed in parallel in a manner analogous to hardware pipelining.

spatial locality
The principle that memory references in a time interval tend to be clustered in the address space. Compare temporal locality.

Special-Purpose Register
A register with a specific function, including an implementation-specific function, that is not fulfilled by a General-Purpose Register (GPR) or a Floating-Point Register (FPR).

speculation
Execution of an instruction before it is known whether the instruction should be executed. Speculative execution may avoid a stall caused by a control hazard. The results of speculative execution must be specially maintained so that the results of mispredicted execution can be eliminated.

SPR
See Special-Purpose Register.

stale
A value older than what should have been obtained.

stall
An instruction in a pipeline cannot proceed. Possible causes of the stall include occupation of the next stage by another instruction, waiting for operands, or serialization. Compare bubble.

static branch prediction
A method in which software (for example, compilers) gives a hint to the processor about the direction the branch is likely to take. See static branch prediction bit.

static branch prediction bit
Bit 4 (y) in the BO field of conditional branch instructions. It provides a hint to the processor about whether the branch is likely to be taken.

static linking
The linking of procedures at compile time, rather than at link time or at load time.

sticky bit
A bit that is set by hardware and remains so until cleared by software.

stride
The relationship between the layout of an array's elements in memory and the order in which those elements are accessed. A stride of length N means that for each array element accessed, N-1 adjacent memory elements are skipped over before the next accessed element.

string
A sequence of characters.

structural hazard
A situation in which the overlapped or out-of-order execution of a pair of instructions generates a conflict between them for a hardware resource.

subroutine
A procedure that does not return a value.

Summary Overflow bit
Bit 0 in the Fixed-Point Exception Register (XER). It indicates an overflow has occurred since this bit was last cleared. When set, bit 3 in a field of the Condition Register (CRn) that is specified in an integer compare instruction is a copy of the SO bit in XER.

supervisor state
The more privileged of the processor's two operating states (the other is problem state, which is the less-privileged user state). Supervisor state is enabled when the problem state (PR) bit in the Machine State Register is 0. In supervisor state, software can access all control registers and the supervisor memory space, as well as execute privileged operations.

synchronization
A software-enforced alteration of the processor state so as to match the program order of instructions. Compare serialization. See also sequential order, program order, context synchronization, and execution synchronization.

system
A combination of processors, storage, and associated mechanisms that is capable of executing programs.

system register
A register accessible only to supervisor (highest-privilege) software.

taken
Conditional branches are "taken" when the condition they are testing is "true".

task
A process (unit of resource ownership) in a multiprogramming (multitasking) environment. A task owns a virtual address space in which it stores processor state, and it may own other resources such as protected access to other processes, I/O devices and files. Compare process, thread and procedure.

temporal locality
The principle that references to a block of memory tend to be clustered in time. Compare spatial locality.

thread
A unit of operating-system scheduling and dispatching that executes sequentially and can be interrupted. Threads are created by processes (tasks), which may own one or more of them, and threads use the resources of the creating process. A thread can be running or waiting to be run. Compare process, procedure and task.

throughput
The number of instructions completed per unit time. Compare latency.

tiny
A floating-point nonzero intermediate result that is less in magnitude than the smallest normalized number of the destination data type.

TLB
See translation-lookaside buffer.

translation-lookaside buffer
An on-chip cache that translates addresses in the virtual address space to addresses in physical memory. The TLB caches the page-table entries for the most recently accessed pages, thereby eliminating the necessity to access the page table from memory during most load/store operations.

trap
An instruction that tests for a specified set of conditions. If any of the tested conditions are met, the system trap handler is invoked.

Trap interrupt
An interrupt that results from the execution of a trap instruction.

UE
See Floating-Point Underflow Exception Enable bit.

update
The action, by a load/store instruction, of automatically copying the target address computed by the instruction into the base register used for the address computation. Update instructions are useful for moving repetitively through data structures.

use-def dependence
See antidependence.

user mode
The least-privileged operating mode. Compare supervisor state. See problem state.

UX
See Floating-Point Underflow Exception bit.

VE
See Floating-Point Invalid Operation Exception Enable bit.

virtual memory
An address space that is larger than its associated physical memory space, but which maps completely to the physical space. The mapping is implemented with a paging mechanism. In paging, unused parts of the virtual memory space are kept in storage (typically disk) that is external to the physical memory, and swapped into physical memory as needed.

volatile register
A register designated by an ABI as unnecessary to save across procedure calls. Also called a caller-save register.

VX
See Floating-Point Invalid Operation Exception Summary bit.

VXCVI
See Floating-Point Invalid Operation Exception (Invalid Integer Convert) bit.

VXIDI
See Floating-Point Invalid Operation Exception ( ÷ ) bit.

VXIMZ
See Floating-Point Invalid Operation Exception ( × 0) bit.

VXISI
See Floating-Point Invalid Operation Exception ( - ) bit.

VXSNAN
See Floating-Point Invalid Operation Exception (SNaN) bit.

VXSOFT
See Floating-Point Invalid Operation Exception (Software Request) bit.

VXSQRT
See Floating-Point Invalid Operation Exception (Invalid Square Root) bit.

VXVC
See Floating-Point Invalid Operation Exception (Invalid Compare) bit.

VXZDZ
See Floating-Point Invalid Operation Exception (0 ÷ 0) bit.

WAR
See write after read.

WAW
See write after write.

word
4 bytes.

write after read
A data hazard in which an instruction attempts to write an operand before a prior instruction has read it, causing the prior instruction to read the wrong data. Compare antidependence.

write after write
A data hazard in which an instruction attempts to write an operand before a prior instruction has written it, leaving the wrong value written. Compare output dependence.

write back
A pipeline stage for the process of writing the result of an instruction back to a register. Compare committed.

XE
See Floating-Point Inexact Exception Enable bit.

XER
See Fixed-Point Exception Register.

XX
See Floating-Point Inexact Exception bit.

y bit
See static branch prediction bit.

ZE
See Floating-Point Zero-Divide Exception Enable bit.

zero extension
The filling of an operand into a wider register or format in which the additional bits are zeros. The resulting destination loses any sign and is typically an unsigned integer. Compare sign extension.

ZX
See Floating-Point Zero-Divide Exception bit.