Foreword

List of Figures

Preface

Purpose and Audience

Code Examples

Contributors

Notation

1. Introduction

1.1 RISC Technologies

1.2 Compilers and Optimization

1.3 Assumptions

2. Overview of the PowerPC Architecture

2.1 Application Environment

2.1.1 32-Bit and 64-Bit Implementations and Modes

2.1.2 Register Resources

2.1.2.1 Branch

2.1.2.2 Fixed-Point

2.1.2.3 Floating-Point

2.1.3 Memory Models

2.1.3.1 Memory Addressing

2.1.3.2 Endian Orientation

2.1.3.3 Alignment

2.1.4 Floating-Point

2.2 Instruction Set

2.2.1 Optional Instructions

2.2.2 Preferred Instruction Forms

2.2.3 Communication Between Functional Classes

2.2.3.1 Fixed-Point and Branch Resources

2.2.3.2 Fixed-Point and Floating-Point Resources

2.2.3.3 Floating-Point and Branch Resources

3. Code Selection

3.1 Control Flow

3.1.1 Architectural Summary

3.1.1.1 Link Register

3.1.1.2 Count Register

3.1.1.3 Condition Register

3.1.2 Branch Instruction Performance

3.1.2.1 Fall-Through Path

3.1.2.2 Needless Branch Register and Recording Activity

3.1.2.3 Condition Register Contention

3.1.3 Uses of Branching

3.1.3.1 Unconditional Branches

3.1.3.2 Conditional Branches

3.1.3.3 Multi-Way Conditional Branches

3.1.3.4 Iteration

3.1.3.5 Procedure Calls and Returns

3.1.3.6 Traps and System Calls

3.1.4 Branch Prediction

3.1.4.1 Default Prediction and Rationale

3.1.4.2 Overriding Default Prediction

3.1.4.3 Dynamic Branch Prediction

3.1.5 Avoiding Branches

3.1.5.1 Computing Predicates

3.1.5.2 Conditionally Incrementing a Value by 1

3.1.5.3 Condition Register Logical

3.2 Integer and String Operations

3.2.1 Memory Access

3.2.1.1 Single Scalar Load or Store

3.2.1.2 Load and Reserve/ Store Conditional

3.2.1.3 Multiple Scalar Load or Store

3.2.1.4 Byte-Reversal Load or Store

3.2.1.5 Cache Touch Instructions

3.2.2 Computation

3.2.2.1 Setting Status

3.2.2.2 Arithmetic Instructions

3.2.2.3 Logical Instructions

3.2.2.4 Rotate and Shift Instructions

3.2.2.5 Compare Instructions

3.2.2.6 Move To/From XER

3.2.3 Uses of Integer Operations

3.2.3.1 Loading a Constant into a Register

3.2.3.2 Endian Reversal

3.2.3.3 Absolute Value

3.2.3.4 Minimum and Maximum

3.2.3.5 Division by Integer Constants

3.2.3.6 Remainder

3.2.3.7 32-Bit Implementation of a 64-Bit Unsigned Divide

3.2.3.8 Bit Manipulation

3.2.3.9 Multiple-Precision Shifts

3.2.3.10 String and Memory Functions

3.3 Floating-Point Operations

3.3.1 Typing, Conversions and Rounding

3.3.2 Memory Access

3.3.2.1 Single-Precision Loads and Stores

3.3.2.2 Double-Precision Loads and Stores

3.3.2.3 Endian Conversion

3.3.2.4 Touch Instructions

3.3.3 Floating-Point Move Instructions

3.3.4 Computation

3.3.4.1 Setting Status Bits

3.3.4.2 Arithmetic

3.3.4.3 Floating-Point Comparison

3.3.5 FPSCR Instructions

3.3.6 Optional Floating-Point Instructions

3.3.6.1 Square Root

3.3.6.2 Storage Access

3.3.6.3 Reciprocal Estimate

3.3.6.4 Reciprocal Square Root Estimate

3.3.6.5 Selection

3.3.7 IEEE 754 Considerations

3.3.7.1 Relaxations

3.3.8 Data Format Conversion

3.3.8.1 Floating-Point to Integer

3.3.8.2 Integer to Floating-Point

3.3.8.3 Rounding to Floating-Point Integer

3.3.9 Floating-Point Branch Elimination

3.3.10 DSP Filters

3.3.11 Replace Division with Multiplication by Reciprocal

3.3.12 Floating-Point Exceptions

4. Implementation Issues

4.1 Hardware Implementation Overview

4.2 Hazards

4.2.1 Data Hazards

4.2.2 Control Hazards

4.2.3 Structural Hazards

4.2.4 Serialization

4.3 Scheduling

4.3.1 Fixed-Point Instructions

4.3.2 Floating-Point Instructions

4.3.3 Load and Store Instructions

4.3.4 Branch Instructions

4.3.5 List Scheduling Algorithm

4.3.6 Common Model

4.3.7 Examples

4.4 Alignment

4.4.1 Loads and Stores

4.4.2 Fetch Buffer

4.4.3 TLB and Cache

5. Clever Examples

5.1 Sign Function

5.2 Transfer of Sign

5.3 Register Exchange

5.4 x = y Predicate

5.5 Clear Least-Significant Nonzero Bit

5.6 Round to a Multiple of a Given Power of 2

5.7 Round Up or Down to Next Power of 2

5.8 Bounds Checking

5.9 Power of 2 Crossing

5.10 Count Trailing Zeros

5.11 Population Count

5.12 Find First String of 1-Bits of a Given Length

5.13 Incrementing a Reversed Integer

5.14 Decoding a "Zero Means 2ⁿ" Field

5.15 2ⁿ in Fortran

5.16 Integer Log Base 10

A. ABI Considerations

A.1 Procedure Interfaces

A.1.1 Register Conventions

A.1.2 Run-Time Stack

A.1.3 Leaf Procedures

A.2 Procedure Calling Sequence

A.2.1 Argument Passing Rules

A.2.2 Function Return Values

A.2.3 Procedure Prologs and Epilogs

A.3 Dynamic Linking

A.3.1 Table Of Contents

A.3.2 Function Descriptors

A.3.3 Out-of-Module Function Calls

B. Summary of PowerPC 6xx Implementations

B.1 Feature Summary

B.2 Serialization

B.2.1 PowerPC 603e Processor Classifications

B.2.2 PowerPC 604 Processor Classifications

B.3 Instruction Timing

B.4 Misalignment Handling

C. PowerPC Instruction Usage Statistics

C.1 By Instruction Category

C.2 By Instruction

C.3 General Information

D. Optimal Code Sequences

D.1 Comparisons and Comparisons Against Zero

D.2 Negated Comparisons and Negated Comparisons Against Zero

D.3 Comparison Operators

D.4 Sign Manipulation

D.5 Comparisons with Addition

D.6 Bit Manipulation

E. Glossary

F. Bibliography and References

F.1 Bibliography

F.2 References

G. Index