Figure 2-1. Application Register Sizes

Figure 2-2. Floating-Point Application Control Fields

Figure 3-1. if-else Code Example

Figure 3-2. C Switch: if-else Code Sequence

Figure 3-3. C Switch: Range Test Code Sequence

Figure 3-4. C Switch: Table Lookup Code Sequence

Figure 3-5. strlen Code Example

Figure 3-6. Branch-On-Count Loop: Simple Code Example

Figure 3-7. Branch-On-Count Loop: Variable Number of Iterations Code Example

Figure 3-8. Branch-On-Count Loop: Variable Range and Stride Code Example

Figure 3-9. Compound Latch Point Code Example

Figure 3-10. Function Call Code Example—C Source

Figure 3-11. Relative Call to foo Code Sequence

Figure 3-12. Call to foo Via Pointer Code Sequence

Figure 3-13. Indirect Subroutine Linkage

Figure 3-14. Conditional Return Code Example

Figure 3-15. Predicate Calculation: Branching Code Sequence

Figure 3-16. Predicate Calculation: Condition-Register Logical Code Sequence

Figure 3-17. Predicate Calculation: Fixed-Point-Operation Code Sequence

Figure 3-18. Arithmetic Expressions for Boolean Predicates

Figure 3-19. Conditionally Incrementing a Value by 1 Code Example

Figure 3-20. Complex Condition Code Example

Figure 3-21. C Switch: Condition Register Logical Code Example

Figure 3-22. Scalar Load Instructions

Figure 3-23. Scalar Store Instructions

Figure 3-24. Endian Reversal of a 4KB Block of Data Code Sequence

Figure 3-25. Absolute Value Code Sequence

Figure 3-26. Unsigned Maximum of a and b Code Sequence

Figure 3-27. Signed Maximum of a and b Code Sequence

Figure 3-28. Signed Divide by 3 Code Sequence

Figure 3-29. Signed Divide by 5 Code Sequence

Figure 3-30. Signed Divide by 7 Code Sequence

Figure 3-31. Signed Divide by -7 Code Sequence

Figure 3-32. Unsigned Divide by 3 Code Sequence

Figure 3-33. Unsigned Divide by 7 Code Sequence

Figure 3-34. Signed Division Magic Number Computation Code Sequence

Figure 3-35. Unsigned Division Magic Number Computation Code Sequence

Figure 3-36. Some Magic Numbers for 32-Bit Operations

Figure 3-37. Some Magic Numbers for 64-Bit Operations

Figure 3-38. 32-Bit Signed Remainder Code Sequence

Figure 3-39. 32-Bit Unsigned Remainder Code Sequence

Figure 3-40. 32-Bit Implementation of 64-Bit Unsigned Division Code Sequence

Figure 3-41. Structure x

Figure 3-42. Code sequences to Extract Bit Fields

Figure 3-43. Code Sequences to Insert Bit Fields

Figure 3-44. Left Shift of a 3-Word Value

Figure 3-45. Code Sequence to Shift 3 Words Left When sh < 64

Figure 3-46. Find Leftmost 0-Byte: Non-Branching Code Sequence

Figure 3-47. Memset Code Sequence with Scalar Store Instructions

Figure 3-48. Convert Floating-Point to 32-Bit Signed Integer Code Sequence

Figure 3-49. Convert Floating-Point to 64-Bit Signed Integer Code Sequence

Figure 3-50. Convert Floating-Point to 32-Bit Unsigned Integer Code Sequence

Figure 3-51. Convert Floating-Point to 64-Bit Unsigned Integer Code Sequence

Figure 3-52. Convert 32-Bit Signed Integer to Floating-Point Code Sequence

Figure 3-53. Convert 64-Bit Signed Integer to Floating-Point Code Sequence

Figure 3-54. Convert 32-Bit Unsigned Integer to Floating-Point Code Sequence

Figure 3-55. Convert 64-Bit Unsigned Integer to Floating-Point Code Sequence

Figure 3-56. Round to Floating-Point Integer Code Sequence

Figure 3-57. Greater Than or Equal to 0.0 Code Example

Figure 3-58. Greater Than 0.0 Code Example

Figure 3-59. Equal to 0.0 Code Example

Figure 3-60. Minimum Code Example

Figure 3-61. a Equal To b Code Example

Figure 3-62. Matrix Product: C Source Code

Figure 3-63. Double-Precision Matrix Product: Assembly Code

Figure 3-64. Convert Division to Multiplication by Reciprocal Code Example

Figure 3-65. Precise Interrupt in Software Code Example

Figure 4-1. Processor Implementations

Figure 4-2. 2-Bit Branch History Table Algorithm

Figure 4-3. Integer Instruction Pipeline

Figure 4-4. Floating-Point Instruction Pipeline

Figure 4-5. Load-Store Instruction Pipeline

Figure 4-6. Pointer Chasing—Load-Use Delay

Figure 4-7. Integer-to-Float Conversion: Load-Store Contention Code Example

Figure 4-8. mtctr Delay: C Switch Code Example

Figure 4-9. mtctr Delay: Call to Function foo Via Pointer Code Example

Figure 4-10. Basic Block Code Example

Figure 4-11. Basic Block Dependence Graph

Figure 4-12. Values for Scheduling Example

Figure 4-13. Scheduled Basic Block Code Example

Figure 4-14. Common Model Instruction Classes

Figure 4-15. Common Model Instruction Delays

Figure 4-16. Simple Scheduling Example with Load-Use Delay Slot

Figure 4-17. Multi-Part Expression Evaluation Scheduling Example

Figure 4-18. Basic Block Code Example: C Code

Figure 4-19. Basic Block Code Example: Scheduled for Common Model

Figure 4-20. Basic Block Code Example: Scheduled for PowerPC 604 Processor

Figure 4-21. Dependent Arithmetic-Conditional Assignments Example

Figure 4-22. Rescheduled Dependent Arithmetic-Conditional Assignments Example

Figure 4-23. Basic Matrix Multiply Kernel Code Example

Figure 4-24. Matrix Multiply Code Example—Scheduled for PowerPC 604 Processor

Figure 4-25. Nested Loops: Touch Instruction Example

Figure 5-1. Sign Function Code Sequence

Figure 5-2. Fortran ISIGN Function Code Sequence

Figure 5-3. Register Exchange Code Sequence

Figure 5-4. "x = y" Predicate Code Sequence

Figure 5-5. Clear Least-Significant Nonzero Bit Code Sequence

Figure 5-6. Test for 0 or a Power of 2 Code Sequence

Figure 5-7. Round Up to a Multiple of 8 Code Sequence

Figure 5-8. Values of flp2(x) and clp2(x)

Figure 5-9. flp2(x) Code Sequence

Figure 5-10. clp2(x) Code Sequence

Figure 5-11. Detect Page Boundary Crossing Code Sequence

Figure 5-12. Count Trailing Zeros Code Sequence

Figure 5-13. Number of Powers of 2 Code Sequence

Figure 5-14. Branch-Free Population Count Code Sequence

Figure 5-15. Branching Population Count Code Sequence

Figure 5-16. Alternative Population Count Code Sequence

Figure 5-17. Detect First String of n 1-Bits Code Sequence

Figure 5-18. Incrementing a Reversed Integer Code Sequence

Figure 5-19. 2ⁿ in Fortran Code Sequence

Figure 5-20. Integer Log Base 10 Code Sequence

Figure A-1. AIX ABI Register Usage Conventions

Figure A-2. Relevant Parts of the Run-Time Stack for Subprogram ccc

Figure A-3. Argument Passing for foo1

Figure A-4. Argument Passing for foo2

Figure A-5. Function Descriptor

Figure A-6. main: Function-Calling Code Example

Figure A-7. ptrgl Routine Code Sequence

Figure A-8. glink_printf Code Sequence

Figure B-1. PowerPC 6xx Processor Features

Figure B-2. Branch Instructions

Figure B-3. Load and Store Instructions

Figure B-4. Cache Control Instructions

Figure B-5. Fixed-Point Computational Instructions

Figure B-6. Floating-Point Instructions

Figure B-7. Optional Instructions

Figure B-8. Number of Accesses for Misaligned Operands

Figure C-1. Instruction Frequency in Integer SPEC92 Benchmarks

Figure C-2. Instruction Frequency in Floating-Point SPEC92 Benchmarks

Figure C-3. Most Frequently Used Instructions in Integer SPEC92 Benchmarks

Figure C-4. Most Frequently Used Instructions in Floating-Point SPEC92 Benchmarks

Figure C-5. PowerPC Instruction Usage in SPEC92 Benchmarks