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[ Table of Contents | Index ]
Appendix G

G. Index


The page numbers for indexed items have no significance in this Web version of The PowerPC Compiler Writer's Guide; they refer only to the hardcopy version. However, each page number has a functional hyperlink to the indexed item.


Numerics

2n in Fortran, 154
32-bit implementation, 5
32-bit mode, 5
64-bit implementation, 5
64-bit mode, 5

A

AA, 9, 209
ABI, 157, 209
absolute value, 50, 205
activation record, 209
add, 46
addi, 46
addic., 46
addis, 46
address, 6, 209
addressing modes, 8
addze, 53
AIX
argument passing rules, 163
function descriptors, 168
function return values, 165
out-of-module function calls, 168
procedure calling sequence, 163
procedure interfaces, 157
procedure prologs and epilogs, 165
Register Conventions, 158
run-time stack, 160
Table Of Contents, 167
algebraic, 209
alias, 209
alignment, 10, 68, 133, 184, 209
load and store, 133
Alignment interrupt, 10, 74, 184
andi., 46, 49
andis., 46
API, 209
argument, 210
atomic, 165, 210

B

B, 210
b, 210
base, 210
base address, 210
basic block, 112, 210
bclr, 19
big-endian, 10, 210
Big-Endian mode, 210
binary point, 210
bit manipulation, 65, 208
Block Address Translation, 210
blocking, 210
bounds checking, 144
branch, 210
absolute, 9, 24
branch-and-link, 210
branch-on-count, 29, 211
conditional, 24
conditional to Count Register, 9
conditional to Link Register, 9
dynamic prediction, 35, 102
folding, 211
instruction performance, 22
multi-way conditional, 25
needless activity, 23
prediction, 18, 35, 102, 172, 211, 214, 230
registers, 7
relative, 9
resolution, 211, 228
scheduling, 110
static prediction, 35, 230
unconditional, 23
unresolved, 18
branch history table, 103
branch target address cache, 102, 211
Branch-Processing Unit, 7, 211
BTAC (see branch target address cache)
bubble, 211
bypass, 101, 211

C

CA (see Carry bit)
cache, 134, 172
block, 211
hit, 211
miss, 106, 211
touch, 134, 211
touch instructions, 45, 75
Carry bit, 46, 212
CIA, 212
clean-up code, 131, 212
clear, 212
clear least-significant nonzero bit, 141
cntlzw, 47
coherence, 212
coherence block, 212
committed, 212
Common Model, 117, 212
compare instructions, 21
compiler, 157, 212
complete, 100, 212
completion unit, 172
computing predicates, 38
condition code, 212
Condition Register, xix, 6, 7, 21, 160, 212
Condition Register contention, 23
Condition Register logical, 40
conditional increment, 39
context, 212
context switch, 103, 212
context synchronization, 213
control flow, 17
conversions, 72
Count Register, 6, 7, 20, 213
count trailing zeros, 145
CPU time, 213
CR (see Condition Register)
CR0:7, 213
CTR (see Count Register)
cycle, 213

D

data
addressing, 9
alignment, 10
decode, 99
decoding a "zero means 2n" field, 153
delay, 112
denormal, 214
denormalized number, 214
dependence, 17, 214
antidependence, 17, 209
control, 17, 213
data, 17, 213
def-def, 213
def-use, 214
name, 17, 223
output, 17, 224
use-def, 231
direct-store segment, 214
dispatch, 99
displacement, 214
division
64-bit unsigned fixed-point, 62
by a power of 2, 52
by integer constants, 51
magic number, 53
replace with multiplication by reciprocal, 92
do loop, 29
double-precision format, 72, 214
doubleword, 214
DSP filters, 92
dynamic branch prediction, 35, 102, 214
dynamic linking, 167, 214
dynamic store forwarding, 214

E

effective address, 214
endian conversion, 75
endian orientation, 10, 214
endian reversal, 49
exception, 214
executable module, 157
execute, 100
execution synchronization, 215
execution time, 112, 175, 215
exponent, 215
extended mnemonic, xx, 215
external cache, 215

F

fall-through path, 23, 215
FE0, FE1 (see Floating-Point Exception mode bits)
fetch, 99, 215
fetch buffer alignment, 134
FEX (see Floating-Point Enabled Exception Summary bit)
FI (see Floating-Point Fraction Inexact bit)
find first string of 1-bits of a given length, 150
first-class value, 215
fixed-point, 215
Fixed-Point Exception Register, 6, 8, 46, 215
Fixed-Point Unit, 7, 104, 215
flat memory, 215
floating-point, 216
Available bit, 216
branch elimination, 86-91
double-precision load and store, 74
Enabled Exception Summary bit, 94, 216
environment controls, 11
Exception Mode bits, 13, 216
Exception Summary bit, 216
exceptions, 93
Floating-Point Status and Control Register, 6, 8, 11, 94, 218
Fraction Inexact bit, 216
Fraction Rounded bit, 216
Inexact Exception bit, 216
Inexact Exception Enable bit, 12, 216
Invalid Operation Exception ( - ) bit, 217
Invalid Operation Exception ( × 0) bit, 217
Invalid Operation Exception ( ÷ ) bit, 216
Invalid Operation Exception (0 ÷ 0) bit, 216
Invalid Operation Exception (Invalid Compare) bit, 217
Invalid Operation Exception (Invalid Integer Convert) bit, 217
Invalid Operation Exception (Invalid Square Root) bit, 217
Invalid Operation Exception (SNaN) bit, 217
Invalid Operation Exception (Software Request) bit, 217
Invalid Operation Exception Enable bit, 12, 216
Invalid Operation Exception Summary bit, 217
move instructions, 75
multiply-add, 79
Non-IEEE Mode bit, 12, 217
operand, 218
Overflow Exception Bit, 217
Overflow Exception Enable bit, 12, 217
Register, 6, 8, 68, 72, 159, 217
Result Flags, 218
Rounding Control, 13, 74, 218
scheduling, 105
single-precision load and store, 74
Underflow Exception bit, 218
Underflow Exception Enable bit, 12, 218
Zero-Divide Exception bit, 218
Zero-Divide Exception Enable bit, 12, 218
Floating-Point Unit, 8, 105, 218
format conversion, 79-86
floating-point to integer, 80
integer to floating-point, 83
rounding to floating-point integer, 85
forwarding, 99, 101, 218
FP (see Floating-Point Available bit)
FPR0:32, 218
FPRF (see Floating-Point Result Flags)
FPSCR (see Floating-Point Status and Control Register)
FPU, 219
FR (see Floating-Point Fraction Rounded bit)
fraction, 219
fres, 77
frsp, 11, 73, 74
frsqrte, 77
FRx, 219
fsel, 78, 86
fsqrt, 77
function, 219
functional class, 5, 219
inter-communication, 14
FX (see Floating-Point Exception Summary bit)

G

General-Purpose Register, 6, 8, 159, 219

H

halfword, 219
hardware overview, 98
hazard, 100, 219
control, 102, 213
data, 100, 213
read after write, 100, 227
structural, 103, 230
write after read, 100, 232
write after write, 100, 233
high, 219
hoist, 219
home location, 219

I

IEEE 754, 5, 11, 78-79, 86, 92, 219
IEEE mode, 219
if-else, 24
immediate operand, 219
implementations, 171
implicit integer bit, 219
imprecise, 220
imprecise interrupt, 220
incrementing a reversed integer, 152
index, 220
indirect, 220
Inexact Exception, 220
inline expansion, 220
instruction, 13
addressing, 8
alignment, 10
arithmetic, 47
compare, 48
Condition Register logical, 22
floating-point arithmetic, 75
floating-point compare, 76
floating-point selection, 78
FPSCR, 76
load, 9
logical, 47
optional, 13, 77
preferred form, 14
queue, 171, 220
reciprocal estimate, 77
reciprocal square root estimate, 77
record, 21
restart, 11, 220
rotate, 47
shift, 47
square root, 77
store, 9
instruction usage statistics, 187
integer
bit position, 220
integer log base 10, 154
interlock, 100, 220
interprocedural analysis, 158, 220
iteration, 28

K

K, 220

L

latch point, 28
latency, 175, 220
LE (see Little-Endian Mode bit)
leaf procedures, 163
least-significant, 221
lifetime analysis, 221
link bit, 7, 19
Link Register, 6, 7, 19, 221
linkage convention, 157, 221
linkage editor, 157, 221
little-endian, 221
Little-Endian Mode bit, 221
LK, 221
load, 43, 221
and reserve, 44
multiple, 45
scheduling, 106
string, 45
with byte-reversal, 45
load and store queue, 109, 172, 173, 222
loader, 157, 221
load-following-store contention, 107, 221
loading a constant into a register, 48
load-store bound, 133, 221
Load-Store Unit, 106, 130, 222
load-use delay, 107, 222
locality, 222
loop
optimization, 130, 222
low, 222
LR, 222
LSB, 222
lsb, 222

M

Machine State Register, 6, 11, 222
machine-dependent optimization, 3, 222
machine-independent optimization, 3, 222
magic number, 51
algorithm, 57
mask, 48, 222
maximum, 51
mcrf, 21
mcrfs, 21, 22
mcrxr, 21, 22, 46
memory, 8, 222
access, 43
addressing, 8
coherence (see coherence)
functions, 68
models, 8
memset, 69
mfcr, 22, 38
mfctr, 23
mffs, 73
mflr, 23
mfspr, 9
minimum, 51
misaligned, 223
miss penalty, 223
MMU, 223
most-significant, 223
MSB, 223
msb, 223
MSR (see Machine State Register)
mtcrf, 22
mtctr, 20, 23
mtlr, 19
mtspr, 9
mtxer, 46, 48
mulld, 47
mulli, 47
mullw, 47
multiple-precision shifts, 66

N

NaN, 223
NI (see Floating-Point Non-IEEE-Mode Enable bit)
NIA, 223
Non-IEEE mode, 12, 79, 223
no-op, 14, 224
normal, 224
normalize, 224
normalized number, 224
Notation, xviii

O

object module, 157, 224
OE (see Floating-Point Overflow Exception Enable bit)
offset, 224
optimization, 3, 224
ordinary segment, 224
out-of-order, 224
OV (see Overflow bit)
overflow, 46, 224
Overflow bit, 46, 224
OX (see Floating-Point Overflow Exception bit)

P

page, 225
path length, 225
pipeline, 99, 225
pipeline stages, 99
pointer, 225
pointer chasing, 107, 225
population count, 146
POWER, 225
power of 2 crossing, 144
PowerPC Little-Endian mode, 10
PR, 225
precise, 225
precise interrupt, 93, 225
precision, 72, 225
predicate, 38, 225
prefetch, 225
preprocessor, 195, 225
privilege level, 226
privilege mechanism, 226
privileged instruction, 226
problem state, 5, 226
procedure, 32, 157, 226
process, 226
processor starvation, 107, 226
profile, 36, 226
program order, 99, 226
protection, 226

Q

quadword, 226
quiet NaN, 227

R

R0:32, 227
range test, 26
RAW (see read after write)
Rc, 227
read, 227
read after write, 100, 227
record, 21, 46, 227
re-entrant, 227
register
allocation, 101, 227
dedicated, 158, 213
exchange, 140
non-volatile, 158, 223
renaming, 101, 172
volatile, 158, 232
registers, 7
remainder, 61
reservation, 44, 227
reservation granule, 44, 227
reservation station, 172, 228
resolution, 18
retire, 228
RISC, 1
rlwinm, 47
RN (see Floating-Point Rounding Control Field)
round to a multiple of a given power of 2, 142
round up or down to next power of 2, 142
rounding, 72
run-time environment, 228
Rx, 228

S

scheduling, 104, 228
searching for the specified byte value, 69
segment, 228
sequential execution model, 99, 228
sequential order, 228
serialization, 104, 174, 228
set, 228
SF (see Sixty-Four Bit Mode bit)
shadow register, 101, 229
sign extension, 229
sign function, 139, 205
signaling NaN, 229
significand, 229
single-precision format, 72, 229
Sixty-Four-Bit mode, 6, 229
SNaN (see signaling NaN)
SO (see Summary Overflow bit)
software pipelining, 229
spatial locality, 229
Special-Purpose Register, 160, 229
speculation, 18, 229
SPR (see Special-Purpose Register)
srawi, 53
stale, 229
stall, 102, 230
static branch prediction, 35, 230
static linking, 170, 230
status bits, 6, 46
floating-point, 75
stfiwx, 77
sticky bit, 230
store, 43
conditional, 44
multiple, 45
scheduling, 106
string, 45
with byte reversal, 45
stride, 31, 230
string, 230
functions, 68
strlen, 29
subf, 46
subroutine, 230
Summary Overflow bit, 230
superscalar, 99
supervisor state, 230
switch, 25
synchronization, 230
system, 230
system register, 231

T

taken, 18, 231
task, 231
temporal locality, 231
thread, 158, 231
throughput, 231
tiny, 231
TLB (see translation-lookaside buffer)
transfer of sign, 140
translation-lookaside buffer, 134, 172, 231
trap, 94, 144, 231
trap interrupt, 94, 231
typing, 72

U

UE (see Floating-Point Underflow Exception Enable bit)
update, 231
user mode, 232
UX (see Floating-Point Underflow Exception bit)

V

VE (see Floating-Point Invalid Operation Exception Enable bit)
virtual memory, 232
VX (see Floating-Point Invalid Operation Exception Summary bit)
VXCVI (see Floating-Point Invalid Operation Exception (Invalid Integer Convert) bit)
VXIDI (see Floating-Point Invalid Operation Exception ( ÷ ) bit)
VXIMZ (see Floating-Point Invalid Operation Exception ( × 0) bit)
VXISI (see Floating-Point Invalid Operation Exception ( - ) bit)
VXSNAN (see Floating-Point Invalid Operation Exception (SNaN) bit)
VXSOFT (see Floating-Point Invalid Operation Exception (Software Request) bit)
VXSQRT (see Floating-Point Invalid Operation Exception (Invalid Square Root) bit)
VXVC (see Floating-Point Invalid Operation Exception (Invalid Compare) bit)
VXZDZ (see Floating-Point Invalid Operation Exception (0 ÷ 0) bit)

W

WAR (see write after read)
WAW (see write after write)
while, 29
word, 232
write after read, 100, 232
write after write, 100, 233
write back, 100, 233

X

x = y predicate, 141
XE (see Floating-Point Inexact Exception Enable bit)
XER (see Fixed-Point Exception Register)
XX (see Floating-Point Inexact Exception bit)

Y

y bit (see static branch prediction bit)

Z

ZE (see Floating-Point Zero-Divide Exception Enable bit)
zero extension, 233
ZX (see Floating-Point Zero-Divide Exception bit)


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Copyright 1998 IBMchips